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  Topic: higher sample rates than 6.9KHz...
damage_x

Replies: 0
Views: 7745

PostForum: General   Posted: Sun Jul 28, 2013 7:44 am   Subject: higher sample rates than 6.9KHz...
Here is my idea. Set the timer interrupt to 874hz (period value of 7). During interrupt routine, stuff 32 PCM samples into the pattern buffer of channel 0, reset timer. On next interrupt, start playin ...
  Topic: interlaced display on PCE?
damage_x

Replies: 2
Views: 12677

PostForum: General   Posted: Sun Jul 28, 2013 7:27 am   Subject: interlaced display on PCE?
very interesting! Sometime I will have to experiment with it more...
  Topic: VDC DMA questions
damage_x

Replies: 4
Views: 15172

PostForum: General   Posted: Mon Feb 20, 2012 1:30 am   Subject: VDC DMA questions
Maybe "???" in the chart above is an additional BAT read to an internal BAT buffer.
What about memory access for sprite graphics? If VDC can display 8 32-pixel-wide sprites per line in 256 ...
  Topic: interlaced display on PCE?
damage_x

Replies: 2
Views: 12677

PostForum: General   Posted: Mon Feb 20, 2012 1:27 am   Subject: interlaced display on PCE?
Has anyone noticed how, when using the 10.7MHz clock, if VDC register 10 is set a certain way the VDC will display every other line? You can then increase the number of lines in register 13 to show a ...
 
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