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interlaced display on PCE?

 
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damage_x
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Joined: 20 Feb 2012
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PostPosted: Mon Feb 20, 2012 1:27 am    Post subject: interlaced display on PCE? Reply with quote

Has anyone noticed how, when using the 10.7MHz clock, if VDC register 10 is set a certain way the VDC will display every other line? You can then increase the number of lines in register 13 to show a larger area or if you leave it at 223 or whatever then the display will wrap mid-screen and start displaying the lines that aren`t seen in the top half.

Sure looks like the workings of an interlaced mode. I made a test ROM image and put it on my flash card and played with the register bits in real time on my TG-16, looking for a way to get the proper v-sync timing for an interlaced mode. But I didn`t really find anything.

Has anyone found a way to modify the timing from the VCE through software? Recently it was discovered on Atari 800 family that a hardware bug which causes it to "forget" the vsync pulse can be manipulated to get a real interlaced mode...

BTW, are bits 0-2 of $0400 already documented somewhere? By the look of it, bit 2 appears to change the phase of chroma carrier every frame or something like that, but there is also some slight difference between setting the bottom bits to 2 or 3.
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Tomaitheous
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PostPosted: Wed Jun 12, 2013 11:07 pm    Post subject: Reply with quote

The VCE reg (normally mapped as $400) has a filter mode for chroma phase shifting. Normally, every other line is like 180* or so out of phase (with matching chroma signal to the burst, obviously), but when you turn on a certain bit in reg $400 (don't remember off hand), it has two effects: the first effect is that it alternates with even and odd scanlines for chroma phase shifting (it takes two frames to complete) and the other is that the display is extended to 263 scanlines instead of 262. With TVs that can handle it, and even most that are poor at handling it - the chroma phase odd/even interleaving swapped on every frame, creates a very clear Y image detail on composite. For non moving stuff, anyway.

As far as the 263 scanline VS 262, nothing really to benefit. But you can make an interlaced display by switching the bit on and off per frame (at the right moment.I used hsync interrupt in the vblank area to do this).



For the VDC skipping scanlines or such (looking like an interlaced setup); it's just a side effect of the VDC timing out on expecting the VCE to generate an interrupt in the hsync reg width. If nothing happens, the VDC starts the next line and outputs, even if the VCE is still on the current line. Of course, when the VCE ends the real scanline, the VDC is forced to shutdown the current scanline and start the next scanline process. So it's possible to setup the VDC that it doesn't so the next scanline on the same VCE/NTSC scanline, but to start it and then have the VCE force another restart. And since the VDC can support up to 525 scanlines or something like that, you'll have enough for a full screen. You just need to set it accordingly.
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damage_x
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PostPosted: Sun Jul 28, 2013 7:27 am    Post subject: Reply with quote

very interesting! Sometime I will have to experiment with it more...
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